Standard capacitor detection and calibration scheme

240KW/400KW industrial rooftop - commercial rooftop - home rooftop, solar power generation system.

The detailed flow chart of the proposed calibration scheme is shown in Fig. 2. First, calibration capacitors are initialized and sampling capacitors are preset by a given code that determines the initial state of the bits under calibration. Subsequently, to guarantee calibration efficiency, comparator offset calibration should be executed prior ...

A 3.66 μW 12-bit 1 MS/s SAR ADC with mismatch and

The detailed flow chart of the proposed calibration scheme is shown in Fig. 2. First, calibration capacitors are initialized and sampling capacitors are preset by a given code that determines the initial state of the bits under calibration. Subsequently, to guarantee calibration efficiency, comparator offset calibration should be executed prior ...

Capacitor mismatch calibration method for SAR ADC with …

Fig. 3 Proposed capacitor mismatches calibration before calibration after calibration ENOB, bits 4 bit improvement mismatch error, % 10–2 14 13 12 11 10 9 10–3 Fig. 4 Monte Carlo simulation with added capacitor mismatches in split-CDAC Capacitor mismatch calibration: Fig. 3 presents the proposed capacitor mismatch calibration logics. It is ...

A real-time digital calibration scheme for the cyclic ADC

A digital calibration scheme to correct the nonlinearity caused by finite amplifier gain and capacitor mismatch for the cyclic analog-to-digital converter (ADC) is presented. The calibration block of correcting the weight of the jumping points is implemented in which adders and registers are utilized without multipliers to reduce the silicon area cost. Each calibration …

(PDF) A capacitor mismatch calibration scheme for SAR ADC …

This calibration technique does not require any extra capacitor DAC and is programmable for any radix-3 SAR ADC. 7 bit Radix-3 ADC is designed which can achieve signal to noise and distortion ...

A low‐cost digital calibration scheme for high‐resolution SAR …

scheme requires less memory to store the calibrated weights and it is implemented in serial architecture to further reduce die size as well as the die cost. Principle of conventional digital calibration using LMS: The conver-sion curve of the SAR ADC which adopts a capacitor array is normally non-linear due to the inevitable capacitor mismatch ...

A 46 μw 13 b 6.4 MS/s SAR ADC with background mismatch and …

IRELESS standards, e.g., 802.15.4g, need high reso-lution ADCs ... statistics-based method to calibrate the capacitor errors in the foreground. However, the statistics-based methods usually have signiﬁcant overhead in latency, area, and power and are thus implemented off-chip. Besides DAC mismatch, noise tends to limit the perfor-mance of high-resolution SAR ADCs in …

A digital background calibration scheme for non-linearity of SAR …

In MATLAB simulation, the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of a 14-bit with 1-bit redundancy SAR ADC model are improved to 85.59 dB and 97.27 dB from 56.65 dB to 77.07 dB using the proposed calibration scheme, at a standard deviation of a unit capacitor of 2%.

An offset calibration scheme for on-chip thermal profiling with ...

This paper introduces an on-chip analog calibration method tailored for differential temperature sensors in thermal monitoring applications. A three-step calibration process is proposed within a two-stage high-gain instrumentation amplifier to compensate for the output voltage offset due to device mismatches and on-chip temperature gradients. The …

An accurate on-site calibration system for electronic voltage ...

Finally, a live connecting scheme is proposed to link the standard capacitor to the HV line. The system can reach class 0.05 accuracy according to the calibration experiment. 2. Principle. According to the IEC standard, the accuracy classes of EVTs are specified as 0.1, 0.2, 0.5, 1 and 3 . In fact, the highest accuracy class of measurement EVTs in operation is …

A Novel Capacitive Detection Scheme With Inherent Self-Calibration

This paper reports a novel capacitive detection method which is robust to variations of such critical parameters as the nominal capacitance, frequency and amplitude of the probing …

A capacitor mismatch calibration scheme for SAR …

In this paper, a new GA-based calibration scheme is proposed with a nonbinary bridged capacitor SAR ADC structure. The proposed calibration scheme aims to improve the linearity deterioration problem …

An offset calibration scheme for on-chip thermal profiling with ...

Sect. 2 introduces the proposed analog calibration scheme for a two-stage IA, Sect. 3 presents the circuit-level design details. Simulation results of the complete dierential tem-perature sensor with proposed oﬀset calibration are covered in Sect. 4. Section 5 draws the conclusion. 2 Proposed oset calibration scheme

Development and Application of 1000 kV Standard Capacitor …

This study describes the development and evaluation of a compact system for onsite calibration of 1000 kV voltage transformers in ultra-high-voltage (UHV) AC power transmission projects and demonstrates the feasibility of an automatic and efficient approach to calibrating UHV Voltage transformers on site.

A Capacitive Mismatch Calibration Method for SAR ADCs Based …

capacitor calibration scheme based on the Time-to-Digital Converter (TDC). This scheme achieves calibration accuracy as high as 0.01n% and can be exibly designed to meet the accuracy requirements of SAR ADCs. Simulation results indicate that the capacitance mismatch issue of a redundant capacitor 13-bit SAR ADC can be completely eliminated, and the e ective …

A capacitive mismatch calibration method for SAR …

To address the capacitance array mismatch in SAR ADCs, this paper proposes a novel capacitor calibration scheme based on the Time-to-Digital Converter (TDC). This scheme achieves calibration accuracy as high …

A novel capacitor recombination calibration method applied to 18 …

The capacitor reconstitution calibration method is introduced with the example of a 14-bit hybrid capacitive–resistive SAR ADC with a high M-bit capacitive DAC and a low N-bit resistive DAC, as shown in Fig. 1.If M = 8 and N = 6, it represents a 14-bit SAR ADC consisting of a high 8-bit capacitive DAC and a low 6-bit resistive DAC. In the mixed resistor-capacitor …

An accurate on-site calibration system for electronic voltage ...

DOI: 10.1088/1361-6501/aaa6a0 Corpus ID: 116712121; An accurate on-site calibration system for electronic voltage transformers using a standard capacitor @article{Hu2018AnAO, title={An accurate on-site calibration system for electronic voltage transformers using a standard capacitor}, author={Chen Hu and Mianzhou Chen and Hongbin Li and Zhu Zhang and Yang …

Analytical Calibrations: Schemes, Manuals, and Metrological ...

This chapter has outlined the process of analytical calibration in terms of appropriate designation (and considering the different releases by different documentary agencies), schemes (multi-, one-, and two-standard calibrations), and the operating manuals. Moreover, the metrological aspects of the calibration process have been revealed throughout …

Capacitor mismatch calibration for SAR ADCs based on …

DOI: 10.1109/ISCAS.2014.6865645 Corpus ID: 18897367; Capacitor mismatch calibration for SAR ADCs based on comparator metastability detection @article{Chen2014CapacitorMC, title={Capacitor mismatch calibration for SAR ADCs based on comparator metastability detection}, author={Long Chen and Ji Ma and Nan Sun}, journal={2014 IEEE International …

Baseline Calibration Scheme Embedded in Single-Slope ADC for …

This paper introduces a single-slope analog-to-digital converter (SS ADC) with an embedded digital baseline calibration scheme designed to improve the accuracy and reliability of gas sensor measurements. The proposed SS ADC effectively leverages an up/down counter mechanism to ensure stable signal extraction from gas sensors, despite variations in the …

Partial Discharge Measurements | Balanced Detection Method

In the modified scheme, another test sample called dummy sample is used in the place of the standard capacitor. The capacitance and tan δ of the dummy sample are made approximately equal, but need not be equal. The disadvantage is that if two discharges occur in both the samples simultaneously, they cancel out, but this is very rare. The main advantage of the …

26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a …

Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellen . 26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme Abstract: Wireless standards, e.g., 802.15.4g, need high-resolution ADCs …

A capacitor mismatch calibration scheme for SAR ADC based on …

novel calibration scheme based on genetic algorithm(GA) combined with a radix-less-than-2 SAR ADC is proposed to extract the weight error caused by capacitor mismatch. This is a …

Capacitor calibration by step-up methods.

prototype standards of length, mass, and time is complex, and for electrical measurements involves meticulous experiments to assign numerical values to calibration standards and …

Capacitance Standards and their Calibration

Selection and calibration of capacitors for use as Standards is a challenging task, especially since the accuracies required, depening on the application, can be very demanding for the test gear as well as for the secondary- and working-standards used. Few capacitance meters are suitable if a higher accuracy needs to be achieved, and also few secondary- and working …

A Novel Capacitive Detection Scheme With Inherent Self-Calibration

In this paper, we develop a novel capacitive detection and self-calibration method that takes advantage of the parallel-plate nonlinearity to eliminate the effect of the nominal capacitance, …

A digital background calibration scheme for non-linearity of SAR …

To verify the linearity calibration of the proposed scheme, a behavioral model of a 14-bit charge redistribution SAR ADC based on CDAC architecture is designed as shown in Fig. 1, which includes KT/C noise and comparator''s noise met the command of 14-bit resolution, as well as the standard deviation of a unit capacitor at 2% and the effect of parasitic …

A 14-bit 1-MS/s SAR ADC with a segmented capacitor

A 14-bit 1-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) for IoT sensing devices is proposed. With a V CM-based switching scheme, the 14-bit SAR ADC can lower 68.7 % switching energy consumption and 97.9 % capacitor array area by utilizing a segmented capacitor array compared to the conventional binary capacitor …

Digital foreground calibration methods for SAR ADCs

and after calibration for the SAR ADC output is shown in Figs. 7 and 8, where a standard DAC capacitance deviation of 0.5 % is assumed. Figure 7. PSD before calibration. Figure 8. PSD after calibration. Without the proposed digital calibration scheme, the PSD plot shows large harmonics. These harmonics are introduced by the DAC capacitor ...

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